We have investigated the design of the 4H-Silicon Carbide Double Implanted Power MOSFET to overcome two challenges.

(i) In the on-state, the presence of high concentration of traps at the 4H-SiC/SiO2 interface and surface roughness lowers the inversion layer mobility drastically. It is shown that the existing on-resistance models which are useful in the design of Si VD (Vertical Diffused) MOSFETs turn highly inaccurate in the case of 4H-SiC DMOSFETs making numerical simulation indispensable for their design. A new method is proposed by which the “inaccurate” analytical Ron models of linear and square cell 4H-SiC DMOSFETs and the simple 2-D simulation of a linear cell can be used to estimate the Ron of a 3-D square cell structure without 3-D simulation.

(ii) In the off-state, field crowding drastically reduces the breakdown voltage of the device from the ideal plane-parallel value. We propose the design of a Floating Field Ring (FFR) based edge termination structure for improving the breakdown voltage of the device and reports a systematic procedure for deriving the number and spacing of the FFRs of any ring length required for achieving an arbitrary breakdown voltage. The procedure is demonstrated considering 1.7–5.5 kV 4H-Silicon Carbide devices and a 700 V Si device reported in literature.