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Hardware-Efficient Algorithms and Architectures for Convolutional  Neural Networks

Hardware-Efficient Algorithms and Architectures for Convolutional Neural Networks

Date9th Apr 2021

Time03:30 PM

Venue Google Meet Link : meet.google.com/auf-etnd-uyx

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Details

With the emergence of deep neural networks and its applications to computer vision problems, the state-of-the art image recognition, segmentation and localization algorithms have achieved very high level of accuracy. In particular, the Convolutional Neural Networks (CNNs) have achieved performance comparable to humans for classifying and detecting objects in an image.

The object classification/detection use-cases, typically require execution of CNN on a portable, low cost and low power consuming device. However, limited computing resources and low on-board memory storage capability of these devices present a challenge for real-time execution of CNN based applications. In this thesis, we present hardware-efficient algorithms to achieve low cost and low power consuming solutions for execution of complex computations in CNN. Further, we present efficient systolic array-based VLSI architectures for execution of CNN.

In this thesis, we also identify the limitations of conventional CNN in detecting occluded objects. We present an algorithm to increase the detection accuracy of the occluded objects, by proposing an enhanced CNN with self-feedback layers. Evaluating the enhanced CNN on a standard benchmark dataset reveals significant increase in precision in detecting occluded objects. Further, the amount of computations required for execution of the enhanced CNN is significantly higher compared to the conventional CNN. We present a hardware-efficient VLSI architecture design for high performance execution of the enhanced CNN.

Speakers

Yashrajsinh Parmar (EE14D200)

Electrical Engineering