The Electric Vehicle (EV) disruption in the auto-motive market is quite evident in the present times. The most of automotive industry is expected to shift towards the 800V EV architecture by 2025. ISO26262 functional safety standard for road vehicles discusses about the development processes and list out the safety requirements for different subsystems. The risks associated for each subsystem are labelled with required Safety Integrity Levels (SIL). The auxiliary DC/DC power converter is used for charging the 48V battery from 800V battery of the EV. The functional safety standard mandates for the Automotive Safety Integrity Level (ASIL) - D rating for the auxiliary DC/DC power converter. This seminar will focus on the development of 8kW, 800V/48V DC/DC power converter with ASIL-D rating. Functional safety is the prime requirement of the automotive market which have been achieved during the development of auxiliary DC/DC power converter. The hardware and software architecture for the DC/DC converter to achieve ASIL-D is ever evolving. The development of compact DSP-FPGA based control board, ASIL-D SiC power module gate driver will be presented in this seminar. The Power Management Integrated Circuit (PMIC) is used in the developed control board for powering the on-board circuits, external boards and it also ensure the safe operation of system.
Shoot-through protection is vital for preventing SiC MOSFET failure during the short circuit event. The Kelvin current sensing based shoot-though protection and DESAT protection for the developed SiC module gate driver board was tested on the Double Pulse Test (DPT) setup. The SPI communication with the gate driver is very important for register initialization, fault monitoring and diagnostics to meet the safety requirements for ASIL-D. So, the novel SPI algorithm is developed in the VHDL environment and the experimental results will be presented which validates the establishment of SPI daisy chain communication with the gate driver.
The converter digital controller is implemented in the FPGA and the development of different soft IP blocks in VHDL will be presented in this seminar. The various faults which lead to failure in the system were analysed using Fault Tree Analysis (FTA) method. The safety mechanisms are implemented in the proposed system architecture for identification of faults within the Fault Detection Time Interval (FTDI) and bring the system into fail-safe state to prevent from failures.