Clock and data recovery (CDR) is essential to serial links catering to high-speed data transfer for a wide range of wireline applications. Knowing the nominal data rate in embedded serial links helps recover the clock frequency with an independent reference clock source on the CDR side. However, clock recovery faces severe challenges in servers and data centers where CDR frequently transitions between data rates and on-and-off states even when the nominal data rate is known. For an energy-efficient data transfer, the power consumption should be proportional to data requirements, and serial links should not operate with the peak data rates if not required. A 2X variation in the peak data rate and rapid on/off (ROO) clock recovery loop facilitates significant energy savings.

In this regard, we present a rapid on/off 0.63-7.5Gb/s digital clock and data recovery with a low turn-on time and recovered clock jitter. The CDR employs a fast-on 1.875-3.75GHz digitally controlled oscillator followed by a 2X integer-N PLL. The DCO incorporates an eight-bit digitally controlled phase interpolator embedded in a 6-12X injection-locked clock multiplier for fast turn-on and low O/P jitter. DCO's O/P is filtered using the fast-on PLL while generating the sampling clock phases for the half-rate CDR. Fabricated in the TSMC 65\,nm process, the CDR recovers the clock with