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Design and analysis of full-duplex multi-gig Ethernet transmitter

Design and analysis of full-duplex multi-gig Ethernet transmitter

Date9th Feb 2022

Time03:00 PM

Venue Google Meet

PAST EVENT

Details

Emerging automotive industry applications require multiple high data rates (Multi-Gig) full-duplex solutions over single-pair Ethernet. This work proposes the optimum modulation scheme and two distinct transceiver architecture modifications based on the IEEE-provided channel data. In the first work, we have presented a full-duplex 3 Gb/s PAM4 voltage-mode transmitter with an embedded 2-tap feed-forward equalizer. In full-duplex mode, the transmitter employs an echo canceller to cancel the locally transmitted signal and recover the signal from the far-end. The 3 Gb/s transmitter achieves energy proportionality with output swings and equalizer coefficients.

In another design, we present a 5 Gb/s PAM4 hybrid voltage-mode transmitter with current mode continuous-time linear equalization (CTLE). The transmitter achieves a large output signal swing with a PAM4 CMOS output driver. A CTLE is embedded in the transmitter’s output stage to compensate for a range of channel loss without reducing the signal swing at the receiver’s front end.

Speakers

Shraman Mukherjee (EE16S058)

Electrical Engineering