GaN based High Electron Mobility Transistors (HEMTs) have shown remarkable performance in high power, high frequency and high operating temperature applications due to its various excellent features e.g., high two-dimensional electron gas (2DEG) mobility, high velocity saturation, high 2DEG concentration, high breakdown voltage, high energy bandgap and ability to withstand the temperature. Apart from conventional AlGaN/GaN HEMT devices AlInN/GaN HEMT devices are also attractive in terms of high 2DEG concentration and high transconductance. Despite all these advantages, GaN based HEMT devices suffer from large gate leakage current (IG) due to polarization induced high barrier electric field. This high IG affects the maximum voltage swing and creates reliability issues in GaN based HEMT devices. Four different current mechanisms, namely Fowler–Nordheim tunneling (FNT), Poole–Frenkel emission (PFE), thermionic emission (TE), and defect-assisted tunneling (DAT) are observed as the main components of IG. FNT and PFE are the two dominant mechanisms in the reverse bias region, while TE and DAT are significant in forward and near zero gate bias regions, respectively. The IG in HEMT can be suppressed significantly in Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) devices due to high barrier height for electron across insulator. The major gate leakage current mechanisms in MIS-HEMT devices are PFE, DAT, trap assisted tunneling (TAT) and FNT. Unlike HEMT, FNT in MISHEMT dominates in the high forward bias region while TAT is the dominant mechanism in moderate forward bias region. PFE always dominates in reverse bias region whereas DAT dominates near zero gate bias region. In our model, IG for MISHEMT device is computed as the sum of the individual components, viz. IFN, ITAT, IDAT and IPF at the given bias conditions. For this purpose, we have derived independent expressions for these current components, which are valid for all bias conditions.

A part of IG flows to the drain terminal as gate-to-drain current (IGD) and the rest flows to the source terminal as gate-to-source current (IGS). For implementation in a circuit simulator, a compact model is required to compute IGD and IGS under different bias conditions. This enables accurate computation of source current (IS) and drain current (ID), including the effect of IG. For this purpose, analytical expressions of drain and source components for different gate current mechanism for HEMT (IyD and IyS, where y = FN, PF, DAT or TE) and MISHEMT (IyD and IyS, where y = FN, TAT, DAT or PF) devices have been derived. This gate current model with the partitioning scheme is implemented in Verilog-A and validated with experimental results for a wide range of gate and drain bias.