Neural-Network implementation on edge devices has necessitated energy-efficient hardware accelerators. In-Memory Computing(IMC) is motivated to alleviate the Von-Neumann bottleneck by avoiding fetching fixed weights from memory and instead performs computation along a bit-line(BL). The voltage developed along a BL is an analog representation of the Multiply-Accumulate(MAC) and needs to be digitized for further processing, placing data-conversion at the heart of IMC, with a focus on pitch-aligned Data Converters(Digital to Analog Converters aligned to word-lines and Analog-Digital Converters(ADC) aligned to data-lines). Flash ADC is the simplest architecture to explore, with prior art using fixed reference voltages generated off-chip. When you consider Neural-Network inference, the range of the MAC is wide across the data set and so fixed references bin coarsely. However, the MAC range narrows significantly for a single input image. We exploit this inherent sub-ranging by using the input image to generate image-dependent reference voltages in an IMC-MAC fashion. We provide an algorithm to populate the bit-cells of the reference column to generate monotone reference voltages. We have taped out a chip and I will summarise the design decisions that went into it and the experiments run on it so far. Future work involves finding in-memory techniques to fix Hardware non-idealities such as variability and Sense-Amp offset.