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Analysis and Design of Analog-to-Digital Converters with Embedded Filtering

Analysis and Design of Analog-to-Digital Converters with Embedded Filtering

Date11th Jun 2021

Time11:00 AM

Venue Google meet



Analog-to-digital converters (ADC) used in wireless applications need to digitize a small desired signal in the presence of large out-of-band interferers. This increases the dynamic range required of the ADC and hence results in significant power dissipation. To attenuate these interferers, it is common practice to place a continuous-time filter ahead of the ADC. However, the filter adds its own noise and distortion to the signal chain. Prior art shows that a CTDSM with an embedded Tow-Thomas filter achieves a better power efficiency, lower area, and higher linearity when compared to the same CTDSM with the filter placed up front. An alternative choice of filter topology, attractive since it uses only one opamp, is the Rauch structure.

In the first part of the talk, we show that embedding a Rauch structure instead of the Tow-Thomas structure, inside the CTDSM is a better design choice. The theory is supported by measurement results from a filtering-CTDSM test chip that achieves a peak SNDR of 76.7dB in a 1MHz signal bandwidth. A novel dummy-switched-DAC is discussed which reduces the effect of parasitics in the feedback DAC references. Measurements demonstrate improved power efficiency and out-of-band linearity when compared to prior art.

The design of CTDSMs for wide bandwidths becomes a challenging task due to large sampling rates required. The excess loop delay of the CTDSM becomes greater than the sampling period rendering the loop unstable. Quantizer metastability is also a serious issue at these speeds. A continuous time pipelined ADC applies the principles of noise-shaping to the pipelined architecture. It is easy to drive thanks to its resistive input impedance, and has inherent anti-aliasing. The second part of the talk presents the architecture and design details of 3-stage CT-pipeline ADC achieving 70 dB SNDR in a 100 MHz bandwidth. It is implemented in a 65nm CMOS process and has a sampling rate of 800 MHz. It incorporates a second order low pass filter that achieves 60 dB rejection in the first Nyquist band. The residue amplifier is implemented using a second order Rauch filter incorporating a 9-level resistive DAC and an RC-delay line. This choice leads to reduced power/area of the ADC and achieves better linearity compared to the state-of-the-art. A 4-X time-interleaved 7b-SAR ADC is used as the back-end. The Schreier and Walden FoM of our ADC is 165.4 dB and 56.1 fJ/level respectively.


Mr. Saravana Kumar (EE14D033)

Electrical Engineering