Wireless applications need power efficient wide-band analog-to-digital converters (ADCs) with high dynamic range. A continuous time delta sigma modulator (CTDSM) is attractive in such applications due to its resistive input impedance as well as implicit antialiasing features. Adopting a CTDSM ADC for wide bandwidths necessitates very high sampling rates in order to achieve desired performance targets. This offers challenges in terms of comparator meta-stability which directly affects loop timing closure as well as data dependent jitter. In addition, high frequency operation is accompanied by increased inter symbol interference (ISI) as well as increased power dissipation. Our work aims to analyse these challenges in detail and offer solutions for overcoming the same.


We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20 MHz signal bandwidth. The modulator, which operates at a sampling rate of 2.56 GHz in a 65nm CMOS process, uses a 2x time-interleaved ADC to address the problem of comparator meta-stability. A 4x time-interleaved virtual-ground-switched resistive FIR feedback DAC is used for low distortion and power-efficient operation. Interleaving artifacts caused by DAC-element mismatch are addressed by mixed signal calibration, which is enabled by the DAC architecture. The decimator is implemented using poly-phase techniques to ease timing constraints and lower power consumption. A prototype modulator, which operates with a 1.1V supply, achieves 82.1 dB peak SNDR and THD of 98.6 dBc while consuming 11.3mW. The resulting Schreier FoM is 174.1 dB.