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Scenario aware Scalable architectures for Digital Communication systems

Scenario aware Scalable architectures for Digital Communication systems

Date6th Apr 2021

Time08:30 AM

Venue Google Meet https://meet.google.com/ifn-npff-zuz

PAST EVENT

Details

Modern wireless communication transceivers operate over a wide range of data rates, bandwidth, modulation schemes, etc. In many cases, they are battery-operated, making low power consumption crucial. The digital baseband section of these devices is designed for worst case operating conditions, whereas typical conditions are often much less harsh. Hence the power consumption remains fairly constant and does not depend on the signal span. In this work, scalable architectures for some of the most commonly used signal processing blocks are proposed whose power consumption can be reduced based on operating scenario. In particular, number representation, dynamic bit width adaptation, input and state encodings, and memory management are shown to be key parameters that can be tuned to reduce power consumption depending on operating conditions.

The concept of dynamic bias addition is proposed in the context of digital filters to modify the toggle activity. The relationship between bit toggles and bias value is studied and the optimal bias value is computed to achieve lowest average bit toggle for a given signal span. This is illustrated using several digital filter architectures, and the application of this concept at the system level is studied in the context of the WLAN receiver.

Scalable bit width architectures are proposed in the context of the Turbo decoder and FFT/IFFT core. In the context of Turbo decoders, the proposed architecture changes include dynamically reducing the bit width across iterations, dynamic scaling of state metrics, and split implementation options for state metric storage memory, which overall lead to scale down the overall power consumption by up to 30% as compared to the conventional implementation. Similarly, in the context of FFT/IFFT cores, proposed re-configurable rounding multipliers and splitting of shift registers into SRAM and flops to enable dynamically scale down the power consumption based on the bit width requirement.

Overall, the thesis systematically analyses the various key factors determining baseband power consumption and shows that with suitable architectural modifications the power consumption can be reduced in a scenario dependent fashion.

Speakers

Sundarrajan Rangachari

Electrical Engineering