The rapid advancement of artificial intelligence (AI) has driven the need for more efficient computing hardware. As traditional approaches relying on Moore's law for device scaling and performance enhancement reach their limits, there is a growing interest in exploring cutting-edge technologies and computational paradigms that can facilitate more efficient information processing. In-memory computing (IMC) is one such approach that aims to enhance performance and energy efficiency by conducting computations directly within the memory elements, thereby minimizing data movement. The crossbar architecture based on Non-Volatile Memories (NVMs) have been extensively studied for IMC to accelerate core operations such as matrix multiplications in tasks such as neural networks, signal processing, and solving differential equations.

Among the various emerging non-volatile memories (eNVMs), ferroelectric memories based on hafnium oxide (HfO2) and ferroelectric field-effect transistors (FeFETs) show promise for the next generation of memory technologies. FeFETs offer several advantages, including field-based operation, low power consumption, fast switching, excellent linearity, bidirectional programmability, good endurance, and compatibility with CMOS technology. However, a significant challenge in implementing FeFET-based computing systems lies in the inherent stochastic behaviour of FeFET devices. Variations in drain currents among FeFETs can negatively impact the performance of a synaptic core, leading to considerable reductions in training and inference accuracy. To address this issue, a memory cell called 1F-1T has been proposed, which consists of a ferroelectric field-effect transistor (FeFET) combined with another current-limiting transistor (T). This additional transistor helps mitigate the effects of ON current (ION) variations by limiting the on-state current in the FeFET. Through system-level simulations of in-memory computing with 1F-1T synapses, the results show promising performance, achieving 97.6% inference accuracy for MNIST handwritten digit recognition using multi-layer perceptron (MLP) neural networks.

Besides matrix multiplications, search operations are also prevalently seen at the core of many applications, and accelerating the searches over a class of data vectors can directly benefit various computational models and improve the system's performance. As a special form of IMC solutions, content addressable memories (CAMs) can accelerate parallel search operations throughout an entire memory array. However, very few analog or multi-bit FeFET-based CAM (FeCAM) designs have been proposed until now. We introduce a 1FeFET-1T multibit CAM design tailored for in-memory search applications. Our FeCAM design stands out as a promising in-memory searching platform when compared to other solutions, mainly due to its straightforward architecture and ability to perform multi-bit operations.