Deep Neural Networks (DNNs) have millions to billions of Multiply-Accumulate (MAC) operations, necessitating energy-efficient hardware accelerators for edge devices. Compute-In-Memory (CIM) alleviates the most energy-hungry step of row-by-row on-chip memory access to the processor. Analog CIMs enable MAC computation along Bit-Lines (BLs) by turning on multiple rows. These BL voltages must be digitized for further digital processing using Analog-Digital Converters (ADCs). Typically, pitch-matching a 4 - 6 bit ADC with a DataLine (DL), a set of 4-8 BLs, is easily implemented in practice. However, an ADC of > 8 bits is required for large-length MACs to get closer to digital precision. It has been demonstrated upon closer investigation that about three-fourths of the ADC’s dynamic range is wasted due to Input Conditioned MAC; i.e., given a single input to a neural network, the MAC range is limited to roughly one-fourth of the overall MAC range. The central focus of this work is to use Input Conditioning to make an N-bit DL ADC look like a configurable N+2-bit ADC. A subtract and amplify circuit is proposed to exploit the inherent input sub-ranging while utilizing the entire dynamic range of the DL-ADC. A modified memory bit-cell is proposed to alleviate mismatch concerns due to the current domain nature of the proposed CIM. An in-memory pitch-aligned calibration technique for the variation prone subtract and amplify circuit is demonstrated. Future work will involve hardware characterization of the fabricated CIM engine and verifying its fidelity to standard DNN models.