Data centre networking demands are growing exponentially because of the emergence of cloud computing and workloads, such as machine learning and artificial intelligence, which require high data throughput. To support these growing bandwidth requirements, new electrical interfaces are being developed to provide a data rate of 112 Gb/s using PAM4 signalling. The key hurdles facing the serializer/deserializer transceiver (SERDES) receiver design for the 112-Gb/s link are related to the need for input signal path circuits with both very high bandwidth and very low noise required for PAM4 signalling. In addition, there must be enough gain and equalization to support long channels. The clock path needs to meet low jitter requirements to allow for accurate sampling. Additionally, in terms of integration, due to the vast number of SERDES channels used in an SOC to support the overall bandwidth, the power efficiency, area, and the lane aspect ratio need to be considered in the design process. To meet these evolving protocol standards and signal integrity requirements of current and future data centre servers, the SERDES equalization capabilities must be flexible, which is inherent to an analog-to-digital converter (ADC)-based architecture, where much of the equalization is shifted to the digital domain. Recent advances in ADC design techniques complement these qualities with attractive power numbers.

High speed SERDES drive the need for high-speed medium-resolution analog-to-digital converters (ADCs) to enable complex digital equalization. Several designs with more than 56 GS/s and at least five ENOB have been reported, which are based on a time-interleaving architecture with successive approximation (SAR) ADCs. To meet the required speed from SAR ADC with medium resolution bits, different architectures are explored to choose the best fit. In this seminar 3-types of SAR ADC architectures will be discussed.