The multi-core processors have been introduced to overcome the limitations of single-core processors, viz excessive power consumption and moderate performance. Improved semiconductor fabrication technology has helped in the large-scale implementation of multi-core processors and many-core processors in place of single-core processors. With additional processor cores, the number of messages between the cores and memories has increased significantly, rendering bus-based communication antiquated. The concept of packet-based communication from computer networks is proposed as an alternative, resulting in on-chip interconnection networks or Network-on-Chip. Each processor core is associated with a router, and these routers are interconnected according to a well-defined topology. The effectiveness of an NoC depends on its topology, routing algorithm, allocation algorithm, flow control mechanism, and router micro-architecture. A simple NoC router consists of buffers, arbiters, allocators, and switches. Simulators and analytical models have been the two primary methods by which the performance of NoC can be analyzed. Analytical models can reduce the time required for design space exploration compared to simulations. Analytical models offer more insight into the operation of NoC. The aim of the thesis is to develop accurate analytical model for the performance analysis of NoC.



In the first part of our research, an analytical model is proposed using a generalized open feed-forward queuing system to estimate the packet latency in an NoC accurately. The packet latency results of the analytical model are validated with simulation results. The packet latency distribution and throughput of our model are compared with simulation results. Performance analysis of NoC carried out for shuffle, tornado, neighbor traffic patterns; Gamma, Generalized Pareto, Weibull, Geometric distributions as injection processes; and XY, West-First, XY-YX routing algorithms. It is shown that our analytical model can achieve significant speedup compared to simulation with minimal error. The standard error of the mean between analytical and simulation models for NoCs with 36 routers is within 10% and is less than 15% for NoCs having up to 64 routers.



In the second part of our work, power and throughput per watt are utilized as the metrics to carry out the power analysis of NoC. A simple router model is adopted to estimate the power consumption of router components such as buffer, arbiter, switch, and clock tree. The observation is that the power consumption of buffers is very high compared to other components of the router. The power consumption values of router components for the latest 10 nm and 7 nm technologies is derived. The effect of switching activity on dynamic power consumption is also explored. Apart from the router power consumption, the power consumption of the overall NoC is also analyzed in several critical situations involving different routing algorithms, traffic patterns. How anlaytial model can be utilized to calculate the power consumption of NoC is also discussed.



The final part of our research involves deriving the injection process characteristics, traffic patterns of PARSEC benchmarks and using them for performance analysis of NoC. The statistical characterization of the PARSEC applications using Q-Q plot and KS test revealed that the inter-arrival process does not match any existing probability distributions. Similarly, the traffic characteristics do not match any of the existing synthetic benchmarks. Two analytical methods are proposed based on Jackson's queuing model and the G/D/1 queuing model. For applications that have exponential arrival and service characteristics, Jackson's model can be used to estimate the latency. For applications exhibiting a general arrival process (for example, PARSEC benchmarks) G/D/1 queuing model has been used for performance analysis. The results of the analytical model are compared with results from the Sniper simulator.