Innovations in materials and device architectures have been driving CMOS device scaling for the last two decades. Traditionally, materials with lower effective mass are expected to outperform silicon channel-based devices because of their higher carrier mobility. However, as channel dimensions scale below 20 nm, quantum mechanical effects like tunneling start to play an increasingly prominent role in determining CMOS device performance. Source to drain tunneling (SDT), where carriers tunnel through the narrow source-channel potential barrier in a short-channel MOSFET, has emerged as a major challenge in further scaling down of the transistor channel length. If not countered, the effects of SDT can completely prevent further scaling down of device dimensions at future technology nodes. The lower effective mass of carriers in alternate channel materials like Germanium (Ge) and III-V materials like Indium Arsenide (InAs), Gallium Arsenide (GaSb) makes them more prone compared to silicon to suffer from excessive leakage due to SDT in OFF-state. Thus, SDT can prevent the integration of non-Silicon channel materials in the future generation of CMOS devices. However, with traditional performance enhancement techniques like using strained silicon nitride capping layers to introduce strain in the channel becoming less effective at small gate length/pitches, it is imperative to look for material options beyond silicon to continue receiving performance improvements with device scaling. Thus for device scaling to continue, the challenge of increased SDT in deeply scaled transistors must be addressed.


A fully quantum mechanical simulation of the impact of SDT in short channel p-MOSFETs has been carried out in this work. Gate-all-around or nanowire MOSFETs have been chosen as the device architecture to scale down transistors, as they provide ultimate electrostatic gate control of the channel. Quantum transport simulations based on the non-equilibrium Green's function (NEGF) formalism have been used to compare the performance of alternate channel materials like Germanium, Gallium Antimonide, Germanium-Tin with silicon as channel materials for p-MOSFETs. Our ballistic quantum transport simulation results show that by suitably choosing the transport orientation, it is possible to minimize the impact of SDT on alternate channel materials and obtain performance improvement over Silicon channel based high-performance devices. The role of source/drain underlaps in countering SDT was also examined. For low power devices, where SDT poses the most severe challenge in scaling down transistor dimensions, alternate channel materials may no longer remain competitive choices compared to Si. The scaling behavior of Silicon channel p-MOSFETs down to a gate length of 10 nm has been investigated. Our simulation results indicate that even with a heavier effective mass of holes, performance improvement of Si devices may not be sustained as the channel length scales down to 5 nm.