Technology scaling over the years has increased the functionality that can be included on a single IC. This scaling has reduced the intrinsic capacitances associated with the transistors and has also usually been accompanied by a reduction in their operating voltages, both of which reduce the energy consumed by a single transistor. However, the massive number of transistors being put on a single IC along with an increase in their operating frequency has caused the overall power consumed by a digital IC to shoot up making power optimization an indispensable part of digital IC design. The active power consumed by an IC is due to the charging and discharging of internal nodes. While functional transitions are necessary for circuit operation, extraneous transitions, called glitches, only lead to unnecessary power consumption. Glitch power can be as high as 70% of the total power for some circuits and warrants reduction if not elimination. Gate sizing is a potential candidate for reducing both functional and glitch power. The problem of gate sizing to meet timing specification while minimizing functional power/area is well understood and is solved by the use of geometric programs (GPs). Traditional area minimization GP (AM-GP) formulations minimize functional power but do not address the problem of glitch power.

In this work, a gate sizing algorithm, Area-Glitch minimization GP (AGM-GP), is proposed to reduce glitches while constraining circuit area and adhering to a timing specification. Glitch reduction is achieved through signal arrival time balancing posed as posynomials in a Geometric Programming formulation. Prior art does not exploit the complete power of gate sizing when reducing glitches in an attempt to meet the timing specification. In particular, the proposed formulation allows both upsizing and downsizing without causing any timing violation, at the expense of a marginal increase in area. Traditional downsizing methods can be used to further reduce glitches over and above the AGM-GP solution. Simulation results on the ISCAS-85 benchmark circuits show an overall reduction of 19.1% glitch power and 8.1% total power which is respectively 13.4% and 3.8% better than just downsizing the AM-GP solution. This power reduction was achieved with an average area increase of 4.2%.

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