Publications
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] Filters: Author is V. Kamakoti [Clear All Filters]
. Delay and peak power minimization for on-chip buses using temporal redundancy. 16th ACM Great Lakes Symposium on VLSI. 2006:119-122.
. Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electronics. 2006;2:425-436.
. A Bus Encoding Technique for Power and Cross-talk Minimization. 17th IEEE International Conference on VLSI Design (VLSI Design 2004). 2004:443-448.
