Course Name: CS6760 : Digital Design Verification

Description: Overview : Introduction to verification, Developing Verification strategies, Applying Verification Strategies, E-standard Programming constructs, RTL ports and Interfaces, Modeling hardware interfaces with Concurrency Constructs, simulating testbenches using Fork-join, stimulus synchronization using conventional synchronization constructs like Mailboxes, Semaphores, regions and events. Hardware Verification Languages : Fundamentals of HVLs, Concurrency Issues, Class definitions and instantiations, tasks and functions, Concurrent techniques, Automatic Stimulus Generation and Randomixed Testing using HVLs, Building Transactors and Stubs, Result Checking, Coverage and Regression, Debugging. Advanced Functional Verification : RTL verification, Processor verification issues, Functional Verification using Constraint modeling. HardwareSoftware Co-verification : Prototyping, Soft/Virtual models, evolving BIST schemes.

Slot: B

RoomNo: CS26

Instructor: Kamakoti V

Period: JAN-MAY 2013

This page was created on: Thursday 19th of September 2013 09:41:55 PM